Embedded systems particularly targeted towards portable applications require extremely low energy consumption as they are often battery powered. In these embedded systems memory consumes a significant portion of the total system power budget; thus memory power reduction is crucial. Lowering supply voltage is one of the options to reduce power (energy) consumption. However, ultra-low-power design of high-density Static Random Access Memory (SRAM) in which the operating voltage is below the transistor threshold voltage is extremely challenging. This is due to reduced static noise margin (SNM) and increased variability in design and process parameters in nanoscale CMOS (nano-CMOS) technology. Therefore, reducing the operating voltage for memory to reduce the leakage power and active energy in energy constraint applications is a major challenge.
In modern System on Chips (SoCs) devices when total power and total area is dominated by the SRAM, reduction in its supply voltage (Vdd) can save both active energy and leakage power during stand-by operation. Hence, supply voltage scaling is the first choice of semiconductor manufacturers for ultra-low-power applications. Also for system integration, SRAM must be compatible with sub-threshold combinational logic operating at ultra-low voltages. However, this leads to an increase in sensitivity of design and process parameter variability. This problem will worsen in nanometer technologies with ultra-low voltage operation and makes SRAM design and stability analysis more challenging.
Process variations have a major impact in both the inter-die and intra-die threshold voltage variation due to random dopant fluctuations in small geometry SRAM cell transistors. Consequently, there are major concerns over SRAM cell stability as well as the integrity of read and write operations in future nano-CMOS designs. This may lead to poor yield and density requirements due to: degraded static noise margin (SNM); poor write-ability; increased sensitivity of design; and severe variations in process parameters. Moreover, the density requirement is mainly limited by the poor driving capacity of bit-lines, which allows fewer cells per bit-line and reduced bit-line sensing margin.
Different types of SRAM bitcells consisting of five, seven, eight, and ten transistors, have been proposed to improve the yield, density and failure probability due to poor SNM, write-ability and process variations.
The 5-transistor bitcell proposed by Carlson et al in “A high density, low leakage, 5T SRAM for embedded caches”, Solid-State Circuits Conference 2004, ESSCIRC 2004, Proceeding of the 30th European, pages 215-218, 21-23 Sep. 2004 employs a single-ended input/output (I/O) line for reading and writing which requires additional sensing circuitry for reliable read operation. In the 7-transistor bitcell proposed by Aly et al in “Novel 7T SRAM cell for low power cache design”, SOC conference, 2005, Proceedings IEEE International, pages 171-174, 19-23 September 2005, a differential read operation is performed, while, during write operations, a feedback connection between inverters is disconnected to improve the read SNM. In the 8-transistor bitcell proposed by Chang et al in “Stable SRAM cell design for the 32 nm node and beyond”, VLSI Technology, 2005. Digest of Technical Papers, 2005 Symposium on, pages 128-129, 14-16 Jun. 2005, two additional NMOS transistors are included to decouple the cell and separate read and write word-lines are used to improve the read stability. A 10-transistor subthreshold bitcell proposed by Calhoun et al in “A 256 kb 65 nm sub-threshold SRAM design for ultra-low voltage operation”, IEEE Journal of Solid-State Circuits, 42(3): 680-688, March 2007 uses a buffer for reading to improve the read SNM. Read access is single ended and employs separate read and write word-lines. A 160 mV robust Schmitt trigger based subthreshold SRAM bitcell proposed by Kulkarni et al in “A 160 mV robust Schmitt trigger based subthreshold SRAM”, Solid State Circuits, IEEE Journal of, 42(10): 2303-2313, October 2007 focuses on making the basic inverter pair of the memory cell robust to improve the stability of the cross-coupled inverters. Here, we will refer to this cell as 10T-ST for subsequent discussions. In the literature, the read SNM of the 7-transistor, 8-transistor and 10-transistor SRAM cells has been improved by decoupling the bitcell nodes from the bit-lines during the read access, hence making the read SNM equal to the hold SNM. However, in 10T-ST, the read SNM has been improved by strengthening the inverter pairs. The write-ability has been improved in prior designs by using virtual supply voltage for write access transistors at the cost of generating and routing an extra supply voltage.
The limitations of current designs motivates the exploration of an alternative SRAM bitcell structure that will be suitable for nano-CMOS circuits for targeted ultra-low-power applications.